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cia.RS = 0x01; |
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cia.RS = 0x01; |
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expect(cia.DATA & 0x40).to.be.equal(0x00); |
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expect(cia.DATA & 0x40).to.be.equal(0x00); |
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}); |
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}); |
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it("Timer B, phi2 Triggered, Interrupt Verification", function(){ |
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let cia = new MOSCIA(); |
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let tick = (cycles) => { |
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for (let i=0; i < cycles; i++) |
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cia.phi2 = 1; |
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}; |
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cia.RS = 0x06; |
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cia.DATA = 0xFF; |
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cia.RS = 0x07; |
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cia.DATA = 0x01; |
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cia.RS = 0x0F; |
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// Force latch load into Timer B and activate Timer B |
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cia.DATA = cia.DATA | 0x11; |
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cia.RS = 0x06; |
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expect(cia.DATA).to.be.equal(0xFF); |
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tick(1); |
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expect(cia.DATA).to.be.equal(0xFE); |
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tick(1); |
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expect(cia.DATA).to.be.equal(0xFD); |
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tick(0x0200 - 3); |
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expect(cia.DATA).to.be.equal(0x00); |
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cia.RS = 0x07; |
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expect(cia.DATA).to.be.equal(0x00); |
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tick(1); |
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expect(cia.DATA).to.be.equal(0x01); |
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cia.RS = 0x06; |
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expect(cia.DATA).to.be.equal(0xFF); |
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cia.RS = 0x0D; |
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let IC = cia.DATA; |
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expect(IC & 0x02).to.be.equal(0x02); |
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expect(IC & 0x80).to.be.equal(0x80); |
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}); |
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it("Timer B, CNT Triggered, Underflow report to Port B", function(){ |
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let cia = new MOSCIA(); |
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let tick = (cycles, cnt) => { |
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cnt = (cnt === true); |
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for (let i=0; i < cycles; i++){ |
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if (cnt) |
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cia.CNT = 1; |
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cia.phi2 = 1; |
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if (cnt) |
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cia.CNT = 0; |
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} |
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}; |
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cia.RS = 0x06; |
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cia.DATA = 0x08; |
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cia.RS = 0x07; |
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cia.DATA = 0x00; |
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cia.RS = 0x0F; |
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// Force latch load into Timer B, |
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// enable underflow reporting on Port B bit 7, |
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// set Timer B to trigger on CNT, |
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// and activate Timer B |
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cia.DATA = 0x33; |
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cia.RS = 0x06; |
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// First, test a few ticks where CNT is not high. |
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expect(cia.DATA).to.be.equal(0x08); // Validate inital timer value. |
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tick(1); |
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tick(1); |
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tick(1); |
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tick(1); |
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expect(cia.DATA).to.be.equal(0x08); |
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// Now verify CNT triggers! |
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tick(1, true); |
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expect(cia.DATA).to.be.equal(0x07); |
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tick(1, true); |
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expect(cia.DATA).to.be.equal(0x06); |
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tick(1, true); |
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tick(1, true); |
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tick(1, true); |
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tick(1, true); |
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tick(1, true); |
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tick(1, true); |
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expect(cia.DATA).to.be.equal(0x00); |
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tick(1, true); |
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// Double check that timer has reset to latch value... |
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expect(cia.DATA).to.be.equal(0x08); |
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// Verify Interrupt (again... but it doesn't hurt!) |
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cia.RS = 0x0D; |
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let IC = cia.DATA; |
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expect(IC & 0x02).to.be.equal(0x02); |
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expect(IC & 0x80).to.be.equal(0x80); |
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// Checking Port B bit 7 which should only go high for 1 cycle! |
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cia.RS = 0x01; |
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expect(cia.DATA & 0x80).to.be.equal(0x80); |
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tick(1, true); |
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expect(cia.DATA & 0x80).to.be.equal(0x00); |
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// Check Port B bit 7 toggling... |
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// ------------------------------------------- |
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// Force latch load into Timer B, |
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// enable underflow reporting on Port B bit 7, |
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// setup Port B bit 7 to invert, |
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// set Timer B to trigger on CNT, |
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// and activate Timer B |
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cia.RS = 0x0F; |
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cia.DATA = 0x37; |
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for (let i=0; i < 9; i++) |
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tick(1, true); |
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cia.RS = 0x06; |
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expect(cia.DATA).to.be.equal(0x08); |
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cia.RS = 0x01; |
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expect(cia.DATA & 0x80).to.be.equal(0x80); |
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tick(1, true); |
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expect(cia.DATA & 0x80).to.be.equal(0x80); |
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cia.RS = 0x06; |
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expect(cia.DATA).to.be.equal(0x07); |
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for (let i=0; i < 8; i++) |
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tick(1, true); |
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expect(cia.DATA).to.be.equal(0x08); |
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cia.RS = 0x01; |
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|
|
expect(cia.DATA & 0x80).to.be.equal(0x00); |
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|
|
|
}); |
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it("Timer B tick on Timer A Underflow (phi2 Triggered)", function(){ |
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|
|
let cia = new MOSCIA(); |
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|
|
let tick = (cycle) => { |
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|
|
for (let i=0; i < cycle; i++) |
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|
|
cia.phi2 = 1; |
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|
|
}; |
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|
|
// Setting up Timer A |
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|
cia.RS = 0x04; |
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cia.DATA = 0x02; |
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|
cia.RS = 0x0E; |
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cia.DATA = 0x11; |
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|
|
// Setting up Timer B |
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cia.RS = 0x06; |
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|
cia.DATA = 0x01; |
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|
cia.RS = 0x0F; |
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cia.DATA = 0x51; |
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|
cia.RS = 0x06; |
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|
|
// Verify Timer B Low Byte Value |
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|
|
expect(cia.DATA).to.be.equal(0x01); |
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|
|
tick(1); |
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|
|
// Timer B should not have changed. |
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|
|
expect(cia.DATA).to.be.equal(0x01); |
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|
|
// Timer A should have ticked down by 1. |
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|
|
cia.RS = 0x04; |
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|
|
expect(cia.DATA).to.be.equal(0x01); |
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|
|
tick(1); tick(1); |
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|
|
// Timer A should have underflowed and Timer B ticked down by 1 |
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|
|
expect(cia.DATA).to.be.equal(0x02); |
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|
|
cia.RS = 0x06; |
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|
|
expect(cia.DATA).to.be.equal(0x00); |
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|
|
// Check that Timer A triggered interrupt... but Timer B did not! |
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|
|
cia.RS = 0x0D; |
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|
|
let IC = cia.DATA; |
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|
|
expect(IC & 0x01).to.be.equal(0x01); |
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|
|
expect(IC & 0x02).to.be.equal(0x00); |
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|
|
tick(3); // Run through Timer A once more. |
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|
|
// Check that both Timer A & B triggered interrupt! |
|
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|
|
IC = cia.DATA; |
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|
|
expect(IC & 0x01).to.be.equal(0x01); |
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|
|
expect(IC & 0x02).to.be.equal(0x02); |
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|
|
// Both timers should have latched back to their starting values. |
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|
|
cia.RS = 0x04; |
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|
|
expect(cia.DATA).to.be.equal(0x02); |
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|
|
cia.RS = 0x06; |
|
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|
|
expect(cia.DATA).to.be.equal(0x01); |
|
|
|
|
|
}); |
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|
|
|
|
|
it("Timer B ticks on Timer A Underflow (CNT Triggered for B only)", function(){ |
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|
|
|
let cia = new MOSCIA(); |
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|
|
|
let tick = (cycle) => { |
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|
|
for (let i=0; i < cycle; i++) |
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|
|
cia.phi2 = 1; |
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|
|
}; |
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|
|
// Setup Timer A (trigger on phi2 only) |
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|
|
cia.RS = 0x04; |
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|
|
cia.DATA = 0x02; |
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|
|
cia.RS = 0x0E; |
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|
|
cia.DATA = 0x11; |
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|
|
// Setup Timer B (trigger on A underflow and CNT high) |
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|
|
cia.RS = 0x06; |
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|
|
cia.DATA = 0x01; |
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|
|
cia.RS = 0x0F; |
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|
|
cia.DATA = 0x71; |
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|
|
// Keep CNT low, check that underflowing A *does NOT* tick B. |
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|
|
cia.CNT = 0; // <-- Just to be sure. |
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|
|
tick(2); |
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|
|
// Just make sure we're ticking A |
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|
|
cia.RS = 0x04; |
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|
|
expect(cia.DATA).to.be.equal(0x00); |
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|
|
tick(1); |
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|
|
expect(cia.DATA).to.be.equal(0x02); |
|
|
|
|
|
// Make sure B did not tick! |
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|
|
|
cia.RS = 0x06; |
|
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|
|
|
expect(cia.DATA).to.be.equal(0x01); |
|
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|
|
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|
|
|
// Clear interrupt flags |
|
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|
|
cia.RS = 0x0D; |
|
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|
|
|
let IC = cia.DATA; |
|
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|
|
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|
|
|
// NOW tick with CNT high! |
|
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|
|
|
cia.CNT = 1; |
|
|
|
|
|
tick(3); |
|
|
|
|
|
// Checking A rolled over |
|
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|
|
|
cia.RS = 0x04; |
|
|
|
|
|
expect(cia.DATA).to.be.equal(0x02); |
|
|
|
|
|
// Now checking B ticked... |
|
|
|
|
|
cia.RS = 0x06; |
|
|
|
|
|
expect(cia.DATA).to.be.equal(0x00); |
|
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|
|
|
// Double check CNT is high |
|
|
|
|
|
expect(cia.CNT).to.be.equal(1); |
|
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|
|
|
|
|
// One more A cycle to check B rolls over! |
|
|
|
|
|
tick(3); |
|
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|
|
|
expect(cia.DATA).to.be.equal(0x01); |
|
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|
|
cia.RS = 0x04; |
|
|
|
|
|
expect(cia.DATA).to.be.equal(0x02); |
|
|
|
|
|
}); |
|
|
}); |
|
|
}); |
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