Added the ROL and ROR opcodes.

src/chip/MOS6502/cpu.js

@@ -136,7 +136,7 @@ function ASL(cpu){
     if (cpu.__ophold === 0){
       cpu.__opv = (mode === 9) ? cpu.__AR : cpu.__opv;
       cpu.C = BITM.val(cpu.__opv, 7);
-      cpu.__opv = cpu.__opv << 1;
+      cpu.__opv = (cpu.__opv << 1) & 0xFF;
       cpu.__ophold = 1;
     } else {
       if (mode === 9){
@@ -496,11 +496,51 @@ function REGISTER(cpu){
 }
 
 function ROL(cpu){
-
+  let pmode = [null, 0x26, 0x36, null, 0x2E, 0x3E, null, null, null, 0x2A].indexOf(cpu.__op);
+  if (cpu.__ophold === 1){pmode = -1;}
+  if (cpu.__ophold === 1 || ProcessOp(cpu, pmode) === true){
+    if (cpu.__ophold === 0){
+      let v = cpu.C; 
+      cpu.__opv = (mode === 9) ? cpu.__AR : cpu.__opv;
+      cpu.C = BITM.val(cpu.__opv, 7);
+      cpu.__opv = ((cpu.__opv << 1) + v) & 0xFF;
+      cpu.__ophold = 1;
+    } else {
+      if (mode === 9){
+        cpu.__AR = cpu.__opv;
+      } else {
+        cpu.__mem.byte = cpu.__opv;
+      }
+      cpu.Z = (this.__opv === 0);
+      cpu.N = BITM.val(this.__opv, 7);
+      cpu.__op = -1;
+      cpu.__ophold = 0;
+    }
+  }
 }
 
 function ROR(cpu){
-
+  let pmode = [null, 0x66, 0x76, null, 0x6E, 0x7E, null, null, null, 0x6A].indexOf(cpu.__op);
+  if (cpu.__ophold === 1){pmode = -1;}
+  if (cpu.__ophold === 1 || ProcessOp(cpu, pmode) === true){
+    if (cpu.__ophold === 0){
+      let v = cpu.C; 
+      cpu.__opv = (mode === 9) ? cpu.__AR : cpu.__opv;
+      cpu.C = BITM.val(cpu.__opv, 0);
+      cpu.__opv = ((cpu.__opv >> 1) + (v * 0x80)) & 0xFF;
+      cpu.__ophold = 1;
+    } else {
+      if (mode === 9){
+        cpu.__AR = cpu.__opv;
+      } else {
+        cpu.__mem.byte = cpu.__opv;
+      }
+      cpu.Z = (this.__opv === 0);
+      cpu.N = BITM.val(this.__opv, 7);
+      cpu.__op = -1;
+      cpu.__ophold = 0;
+    }
+  }
 }
 
 function RTI(cpu){