| const IO = require('./common/io.js'); | |||||
| const BCD = require('./utils/bcd.js'); | const BCD = require('./utils/bcd.js'); | ||||
| const BITM = require('./utils/bitman.js'); | const BITM = require('./utils/bitman.js'); | ||||
| class MOSCIA{ | class MOSCIA{ | ||||
| constructor(){ | constructor(){ | ||||
| this.__io = new IO(["PDA", "PDB"], ["PDA", "PDB"]); | |||||
| this.__regsel = 0; | this.__regsel = 0; | ||||
| this.__RW = 0; | this.__RW = 0; | ||||
| let val = 0; | let val = 0; | ||||
| switch(this.__regsel){ | switch(this.__regsel){ | ||||
| case 0x00: // Peripheral Data A | case 0x00: // Peripheral Data A | ||||
| break; | |||||
| this.__io.triggerRead("PDA", this.__DDA); | |||||
| val = this.__PDA; break; | |||||
| case 0x01: // Peripheral Data B | case 0x01: // Peripheral Data B | ||||
| break; | |||||
| this.__io.triggerRead("PDB", this.__DDB); | |||||
| val = this.__PDB; break; | |||||
| case 0x02: // Data Direction Reg A | case 0x02: // Data Direction Reg A | ||||
| break; | |||||
| val = this.__DDA; break; | |||||
| case 0x03: // Data Direction Reg B | case 0x03: // Data Direction Reg B | ||||
| break; | |||||
| val = this.__DDB; break; | |||||
| case 0x04: // Timer A Low | case 0x04: // Timer A Low | ||||
| val = (this.__timerA & 0x00FF); break; | val = (this.__timerA & 0x00FF); break; | ||||
| case 0x05: // Timer A High | case 0x05: // Timer A High | ||||
| let tod = 0; | let tod = 0; | ||||
| switch(this.__regsel){ | switch(this.__regsel){ | ||||
| case 0x00: // Peripheral Data A | case 0x00: // Peripheral Data A | ||||
| this.__io.triggerWrite("PDA", this.__PDA, d & 0xFF); | |||||
| this.__PDA = (this.__PDA & (~this.__DDA)) | ((d & 0xFF) & this.__DDA); | |||||
| break; | break; | ||||
| case 0x01: // Peripheral Data B | case 0x01: // Peripheral Data B | ||||
| this.__io.triggerWrite("PDB", this.__PDB, d & 0xFF); | |||||
| this.__PDB = (this.__PDB & (~this.__DDB)) | ((d & 0xFF) & this.__DDB); | |||||
| break; | break; | ||||
| case 0x02: // Data Direction Reg A | case 0x02: // Data Direction Reg A | ||||
| this.__DDA = d & 0xFF; | |||||
| break; | break; | ||||
| case 0x03: // Data Direction Reg B | case 0x03: // Data Direction Reg B | ||||
| this.__DDB = d & 0xFF; | |||||
| break; | break; | ||||
| case 0x04: // Timer A Low | case 0x04: // Timer A Low | ||||
| this.__timerALatch = (this.__timerALatch & 0xFF00) | (d & 0xFF); | this.__timerALatch = (this.__timerALatch & 0xFF00) | (d & 0xFF); | ||||
| } | } | ||||
| } | } | ||||
| onRead(name, fn){ | |||||
| this.__io.onRead(name, fn); | |||||
| return this; | |||||
| } | |||||
| onWrite(name, fn){ | |||||
| this.__io.onWrite(name, fn); | |||||
| return this; | |||||
| } | |||||
| setPDA(v){ | |||||
| this.__PDA = (this.__PDA & this.__DDA) | ((v & 0xFF) & (~this.__DDA)); | |||||
| return this; | |||||
| } | |||||
| setPDB(v){ | |||||
| this.__PDB = (this.__PDB & this.__DDB) | ((v & 0xFF) & (~this.__DDB)); | |||||
| return this; | |||||
| } | |||||
| reset(){ | reset(){ | ||||
| this.__CNT = 0; | this.__CNT = 0; | ||||
| this.__TOD = [0,0,0,0]; | this.__TOD = [0,0,0,0]; | ||||
| this.__LTOD = [0,0,0,0]; | this.__LTOD = [0,0,0,0]; | ||||
| this.__ALTOD = [0,0,0,0]; | this.__ALTOD = [0,0,0,0]; | ||||
| return this; | |||||
| } | } | ||||
| } | } | ||||