Fixed the order of the status register flags and initialized the status register to 32 (bit 5 on).

src/chip/MOS6502/cpu.js

@@ -348,26 +348,26 @@ class CPU{
 
   // ----------------------------------------
   // Quick Flag Access
-  get N(){return (BIT.isOn(this.__PR, 0)) ? 1 : 0;}
-  set N(n){this.__PR = (n === true || n === 1) ? BIT.set(this.__PR, 0) : BIT.clear(this.__PR, 0);}
+  get N(){return (BIT.isOn(this.__PR, 7)) ? 1 : 0;}
+  set N(n){this.__PR = (n === true || n === 1) ? BIT.set(this.__PR, 7) : BIT.clear(this.__PR, 7);}
 
-  get V(){return (BIT.isOn(this.__PR, 1)) ? 1 : 0;}
-  set V(v){this.__PR = (v === true || v === 1) ? BIT.set(this.__PR, 1) : BIT.clear(this.__PR, 1);}
+  get V(){return (BIT.isOn(this.__PR, 6)) ? 1 : 0;}
+  set V(v){this.__PR = (v === true || v === 1) ? BIT.set(this.__PR, 6) : BIT.clear(this.__PR, 6);}
 
-  get B(){return (BIT.isOn(this.__PR, 3)) ? 1 : 0;}
-  set B(b){this.__PR = (b === true || b === 1) ? BIT.set(this.__PR, 3) : BIT.clear(this.__PR, 3);}
+  get B(){return (BIT.isOn(this.__PR, 4)) ? 1 : 0;}
+  set B(b){this.__PR = (b === true || b === 1) ? BIT.set(this.__PR, 4) : BIT.clear(this.__PR, 4);}
 
-  get D(){return (BIT.isOn(this.__PR, 4)) ? 1 : 0;}
-  set D(d){this.__PR = (d === true || d === 1) ? BIT.set(this.__PR, 4) : BIT.clear(this.__PR, 4);}
+  get D(){return (BIT.isOn(this.__PR, 3)) ? 1 : 0;}
+  set D(d){this.__PR = (d === true || d === 1) ? BIT.set(this.__PR, 3) : BIT.clear(this.__PR, 3);}
   
-  get I(){return (BIT.isOn(this.__PR, 5)) ? 1 : 0;}
-  set I(i){this.__PR = (i === true || i === 1) ? BIT.set(this.__PR, 5) : BIT.clear(this.__PR, 5);}
+  get I(){return (BIT.isOn(this.__PR, 2)) ? 1 : 0;}
+  set I(i){this.__PR = (i === true || i === 1) ? BIT.set(this.__PR, 2) : BIT.clear(this.__PR, 2);}
 
-  get Z(){return (BIT.isOn(this.__PR, 6)) ? 1 : 0;}
-  set Z(z){this.__PR = (z === true || z === 1) ? BIT.set(this.__PR, 6) : BIT.clear(this.__PR, 6);}
+  get Z(){return (BIT.isOn(this.__PR, 1)) ? 1 : 0;}
+  set Z(z){this.__PR = (z === true || z === 1) ? BIT.set(this.__PR, 1) : BIT.clear(this.__PR, 1);}
 
-  get C(){return (BIT.isOn(this.__PR, 7)) ? 1 : 0;}
-  set C(c){this.__PR = (c === true || c === 1) ? BIT.set(this.__PR, 7) : BIT.clear(this.__PR, 7);}
+  get C(){return (BIT.isOn(this.__PR, 0)) ? 1 : 0;}
+  set C(c){this.__PR = (c === true || c === 1) ? BIT.set(this.__PR, 0) : BIT.clear(this.__PR, 0);}
 
   // ----------------------------------------
   // Hardware interrupt triggers. Settable only.