|
|
@@ -357,7 +357,7 @@ describe("MOSCIA Tests...", function(){ |
|
|
|
expect(IC & 0x80).to.be.equal(0x80); |
|
|
|
}); |
|
|
|
|
|
|
|
it("Timer A", function(){ |
|
|
|
it("Timer A, phi2 Triggered, Interrupt Verification", function(){ |
|
|
|
let cia = new MOSCIA(); |
|
|
|
let tick = (cycles) => { |
|
|
|
for (let i=0; i < cycles; i++) |
|
|
@@ -393,6 +393,99 @@ describe("MOSCIA Tests...", function(){ |
|
|
|
expect(IC & 0x01).to.be.equal(0x01); |
|
|
|
expect(IC & 0x80).to.be.equal(0x80); |
|
|
|
}); |
|
|
|
|
|
|
|
|
|
|
|
it("Timer A, CNT Triggered, Underflow report to Port B", function(){ |
|
|
|
let cia = new MOSCIA(); |
|
|
|
let tick = (cycles, cnt) => { |
|
|
|
cnt = (cnt === true); |
|
|
|
for (let i=0; i < cycles; i++){ |
|
|
|
if (cnt) |
|
|
|
cia.CNT = 1; |
|
|
|
cia.phi2 = 1; |
|
|
|
if (cnt) |
|
|
|
cia.CNT = 0; |
|
|
|
} |
|
|
|
}; |
|
|
|
|
|
|
|
cia.RS = 0x04; |
|
|
|
cia.DATA = 0x08; |
|
|
|
cia.RS = 0x05; |
|
|
|
cia.DATA = 0x00; |
|
|
|
|
|
|
|
cia.RS = 0x0E; |
|
|
|
// Force latch load into Timer A, |
|
|
|
// enable underflow reporting on Port B bit 6, |
|
|
|
// set Timer A to trigger on CNT, |
|
|
|
// and activate Timer A |
|
|
|
cia.DATA = 0x33; |
|
|
|
|
|
|
|
cia.RS = 0x04; |
|
|
|
// First, test a few ticks where CNT is not high. |
|
|
|
expect(cia.DATA).to.be.equal(0x08); // Validate inital timer value. |
|
|
|
tick(1); |
|
|
|
tick(1); |
|
|
|
tick(1); |
|
|
|
tick(1); |
|
|
|
expect(cia.DATA).to.be.equal(0x08); |
|
|
|
|
|
|
|
// Now verify CNT triggers! |
|
|
|
tick(1, true); |
|
|
|
expect(cia.DATA).to.be.equal(0x07); |
|
|
|
tick(1, true); |
|
|
|
expect(cia.DATA).to.be.equal(0x06); |
|
|
|
tick(1, true); |
|
|
|
tick(1, true); |
|
|
|
tick(1, true); |
|
|
|
tick(1, true); |
|
|
|
tick(1, true); |
|
|
|
tick(1, true); |
|
|
|
expect(cia.DATA).to.be.equal(0x00); |
|
|
|
tick(1, true); |
|
|
|
|
|
|
|
// Double check that timer has reset to latch value... |
|
|
|
expect(cia.DATA).to.be.equal(0x08); |
|
|
|
|
|
|
|
// Verify Interrupt (again... but it doesn't hurt!) |
|
|
|
cia.RS = 0x0D; |
|
|
|
let IC = cia.DATA; |
|
|
|
expect(IC & 0x01).to.be.equal(0x01); |
|
|
|
expect(IC & 0x80).to.be.equal(0x80); |
|
|
|
|
|
|
|
// Checking Port B bit 6 which should only go high for 1 cycle! |
|
|
|
cia.RS = 0x01; |
|
|
|
expect(cia.DATA & 0x40).to.be.equal(0x40); |
|
|
|
tick(1, true); |
|
|
|
expect(cia.DATA & 0x40).to.be.equal(0x00); |
|
|
|
|
|
|
|
// Check Port B bit 6 toggling... |
|
|
|
// ------------------------------------------- |
|
|
|
// Force latch load into Timer A, |
|
|
|
// enable underflow reporting on Port B bit 6, |
|
|
|
// setup Port B bit 6 to invert, |
|
|
|
// set Timer A to trigger on CNT, |
|
|
|
// and activate Timer A |
|
|
|
cia.RS = 0x0E; |
|
|
|
cia.DATA = 0x37; |
|
|
|
|
|
|
|
for (let i=0; i < 9; i++) |
|
|
|
tick(1, true); |
|
|
|
cia.RS = 0x04; |
|
|
|
expect(cia.DATA).to.be.equal(0x08); |
|
|
|
|
|
|
|
cia.RS = 0x01; |
|
|
|
expect(cia.DATA & 0x40).to.be.equal(0x40); |
|
|
|
tick(1, true); |
|
|
|
expect(cia.DATA & 0x40).to.be.equal(0x40); |
|
|
|
cia.RS = 0x04; |
|
|
|
expect(cia.DATA).to.be.equal(0x07); |
|
|
|
|
|
|
|
for (let i=0; i < 8; i++) |
|
|
|
tick(1, true); |
|
|
|
expect(cia.DATA).to.be.equal(0x08); |
|
|
|
cia.RS = 0x01; |
|
|
|
expect(cia.DATA & 0x40).to.be.equal(0x00); |
|
|
|
}); |
|
|
|
}); |
|
|
|
|
|
|
|
|