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@@ -22,7 +22,45 @@ function BIT(cpu){ |
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} |
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function BRANCH(cpu){ |
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switch(cpu.__step){ |
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case 0: |
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cpu.__mem.address = this.__PC; |
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let v = cpu.__mem.byte; |
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cpu.__opv = v; |
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break; |
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case 1: |
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let branch = false; |
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switch(cpu.__op){ |
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case 0x10: // BPL |
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branch = (cpu.N === 0); break; |
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case 0x30: // BMI |
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branch = (cpu.N === 1); break; |
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case 0x50: // BVC |
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branch = (cpu.V === 0); break; |
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case 0x70: // BVS |
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branch = (cpu.V === 1); break; |
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case 0x90: // BCC |
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branch = (cpu.C === 0); break; |
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case 0xB0: // BCS |
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branch = (cpu.C === 1); break; |
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case 0xD0: // BNE |
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branch = (cpu.Z === 0); break; |
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case 0xF0: // BEQ |
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branch = (cpu.Z === 1); break; |
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} |
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if (branch === false) |
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PCUp(cpu, 1); |
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case 2: |
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if (cpu.__step === 2){ |
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if (cpu.__opv > 128){ |
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PCDown(cpu, 255 - cpu.__opv); |
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} else { |
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PCUp(cpu, cpu.__opv); |
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} |
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} |
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cpu.__op = -1; |
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} |
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cpu.__step += 1; |
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} |
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function BRK(cpu){ |
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@@ -201,12 +239,22 @@ class CPU{ |
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// ---------------------------------------- |
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// CPU Registers. Here for debug purposes. |
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get PC(){return this.__PC;} |
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get P(){return this.__SR;} |
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get P(){return this.__PR;} |
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get X(){return this.__XR;} |
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get Y(){return this.__YR;} |
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get A(){return this.__AR;} |
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// ---------------------------------------- |
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// Quick Flag Access |
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get N(){return (BIT.isOn(this.__PR, 0)) ? 1 : 0;} |
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get V(){return (BIT.isOn(this.__PR, 1)) ? 1 : 0;} |
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get B(){return (BIT.isOn(this.__PR, 3)) ? 1 : 0;} |
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get D(){return (BIT.isOn(this.__PR, 4)) ? 1 : 0;} |
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get I(){return (BIT.isOn(this.__PR, 5)) ? 1 : 0;} |
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get Z(){return (BIT.isOn(this.__PR, 6)) ? 1 : 0;} |
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get C(){return (BIT.isOn(this.__PR, 7)) ? 1 : 0;} |
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// ---------------------------------------- |
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// Hardware interrupt triggers. Settable only. |
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set NMI(n){ |
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this.__nmi = (n === true); |
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@@ -254,6 +302,7 @@ class CPU{ |
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} |
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} else { |
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this.__step = 0; |
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this.__mem.address = this.__PC; |
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this.__op = this.__mem.byte; |
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PCUp(this, 1); |
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} |